1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit structures and fabrication processes.
2. Description of the Background Art
An integrated circuit typically includes multiple sections for performing various functions. The sections may be on one level of an integrated circuit, or in separate levels. A conductive line, commonly referred to as an interconnect line, electrically couples two or more sections that are on the same level of the integrated circuit. To couple sections that are on different levels, a via is provided between the levels. The via is filled with a conductive material. One end of the via is coupled to an interconnect line on an upper level, while the other end of the via is coupled to an interconnect line on a lower level. A dielectric layer is provided between levels for electrical isolation.
The speed at which a signal is propagated in an integrated circuit is limited by the delay through the interconnect line carrying the signal. This delay, commonly referred to as “RC delay,” is due to the resistance and capacitance of the interconnect line. Reducing the resistance or capacitance of the interconnect line lowers its RC delay and increases signal propagation speed. Thus, reducing the RC delay of interconnect lines plays a major role in making integrated circuits run faster.
Using a low-resistance interconnect material such as copper helps lower the resulting RC delay. To reduce capacitance, a dielectric material having a low dielectric constant, referred to as a low-k dielectric, may be used between interconnect lines or layers.
A low-k dielectric region may be formed by using a TEOS oxide to fill gaps between metal lines. The inability of the TEOS oxide to completely fill the gaps results in air gaps between the metal lines. Because air has a dielectric constant of 1, the resulting air gaps help lower capacitance. However, the formation of the resulting air gaps is not controllable, and their size varies depending on the metal etch profile and available space. Additionally, the TEOS oxide fills the space between metal layers. Various relatively complicated unity-k dielectric structures have also been proposed to lower capacitance on metal lines.